This application relies for priority upon Korean Patent Application No. 1999-55215, filed on Dec. 6, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a semiconductor memory device and, more particularly, to a sense amplifier circuit applied to a semiconductor memory device.
The more densely memory devices are integrated, the more memory cells therein are shrunk. This causes current drivability of the memory cell to be degraded.
In a semiconductor memory device taken in a portable electric apparatus operable with a low voltage, a memory cell current required to sense data is even more degraded, because the device is operating at a very low voltage. When the current flowing through a memory cell becomes less, an operation speed of a sense amplifier circuit for sensing a state of the memory cell become slower, due to the weak current drivability of the memory cell. As a result, an overall accessing time of the semiconductor memory device becomes longer.
The facility of a sense amplifier circuit greatly affects the performance of the semiconductor memory device. Such is made more clear from the below.
Referring to FIG. 1, a sense amplifier circuit is constructed with a differential amplifier that senses and amplifies a voltage difference between two input signals. The differential amplifier can include two input transistors, a current sink (composed of a MOS transistor) serially coupled to the input transistors, and a current mirror. An input voltage to be sensed is applied to a control gate of one of the input transistors. The input of the sense amplifier is decided by a cell current flowing through a cell (xe2x80x9con-cellxe2x80x9d or xe2x80x9coff-cellxe2x80x9d).
In the conventional sense amplifier circuit of FIG. 1, one input terminal of a differential amplifier 12 is coupled to a node DSO (hereinafter referred to as xe2x80x9creference nodexe2x80x9d) to which a dummy load (or current source) 14 and a dummy cell 18 are coupled, respectively. The other input terminal of the differential amplifier 12 is coupled to a node S0 (hereinafter referred to as xe2x80x9cinput nodexe2x80x9d) to which a main node 16 and a memory cell 20 are coupled, respectively. The dummy cell 18 is constructed to maintain an intermediate current drivability that is between those of the one-cell and the off-cell.
The operation is now described also with reference to FIG. 2. It is first assumed that both the dummy load 14 and the main load 16 supply the same amount of current as flows through the dummy cell 18. When a read operation is started, voltages (i.e., the reference voltage and input voltage) of the nodes DS0 and S0 gradually increase by an amount of current that is supplied through the corresponding loads 14 and 16. After a predetermined time T2, the voltage of the reference node DS0 stabilizes at its initial level, while that of the input node S0 diverges.
More particularly, the voltage level at input node S0 follows a state (an on-cell or an off-cell) of a memory cell. For example, if the memory cell 20 is an on-cell, the input voltage becomes lower than the reference voltage. On the other hand, if the memory cell 20 is an off-cell, the input voltage becomes higher than the reference voltage. The differential amplifier 12 senses the voltage different between the input and reference voltages. Depending upon the sensed result, a signal OUT with high or low level is generated from the sense amplifier circuit 10.
The reference voltage of the reference node DS0 and the input voltage of the sensing node S0 are created at the same time. Namely, at the beginning of the read operation, the voltages of the nodes DS0 and S0 are set to required voltage levels.
Then, the sensing operation is started to compare the input responding to a state of the memory cell with the reference voltage. The sensing operation takes place long enough after divergence has started, so as to secure a comfortable sensing margin.
In real applications, there are problems caused by capacitance imbalance between the reference and sensing nodes that are the input terminals DS0, S0 of the differential amplifier 12. Such problems include performance degradation of the sense amplifier circuit, and cannot be easily solved by conditioning circuit design parameters with stably predictable features.
Continuing to refer to FIG. 2, if a load at the reference node DS0 is greater than that at the sensing node S0, the actual rise time will be T1 instead of T2 (following the dashed line). This will not give enough opportunity to the voltages of the nodes DS0 and S0 to diverge enough from each other, so as to secure a stable sensing margin of a sense amplifier circuit. This prevents a read operation from being stable, which can result in read-out failure in the worst case.
It is an object of the invention to provide a semiconductor memory device capable of stabilizing a sensing operation.
It is another object of the invention to provide a semiconductor memory device capable of preventing read-out failure caused by a discord of set-up timing between a reference voltage and an input voltage of a sense amplifier.
According to one aspect of the present invention, a semiconductor memory device includes a memory cell array in which rows and columns are arranged. The semiconductor memory device includes at least one dummy cell, a sense amplifier circuit, and a sense amplifier controller. The sense amplifier circuit is coupled to the dummy cell, and internally generates a reference voltage in response to first control signals. The sense amplifier controller generates first and second control signals during a read operation. The first control signals are enabled before the second control signals are enabled, such that the reference voltage is set to constant voltage level. The sense amplifier circuit senses data stored in the selected memory cells in response to the reference voltage and to the second control signals.
According to another aspect of the present invention, there is a method of reading data stored in a semiconductor memory device that includes a memory cell array in which rows and columns are arranged, and a sense amplifier circuit for sensing a state of a selected memory cell. A reference voltage is generated using a dummy cell coupled to the sense amplifier circuit, and is set to constant voltage level. Then, a state of the selected memory cell is sensed in response to the reference voltage.